Yevgeni Tunik

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Embedded Software Engineer

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    • Too many common words. Too little real information.

    • It's doubtful, that even regular IT security solutions were implemented during as-soon-as-possible official launching of the national pride object at the country, which is governed by the fanatic regime. Note, that the civilized countries, which use the same Siemens industrial controllers, have no significant damage. Sure, the technical culture is catastrofic after so many years of total conflict with the civilized world. A western engineer typically cannot imagine, how the thinking can be distorted with above style of life.

    • Bottom line of the article: MIPS parameter shows performance of CPU for ideal case of the full CPU load. Most the real control tasks are too far from this assumption due to peripherals, SDRAM or DDRAM, cashe, etc. By the way, the computer literature typically estimates performance of general purpose CPUs using some typical applications: fixed point calculations, floating point calculations, etc. MIPS parameter is especially useful for comparison of CPUs of the same architecture. For example, for selecting another microcontroller of Coldfire family with two time more fast clock, it's reasonable to expect improving the FFT time twice. Also MIPS parameter is useful for estimating the CPU time of pure calculations, similar to digital filter.

    • Calculation of timing requirements for the SPI example assumes non-realistic SPI controller. The real-life peripherals have some simple hardware features to improve the system performance. The typical SPI controller has double-buffering, which allows the management interval of transferring 2 bytes. Thus, the interrupt has 2 us to transfer 16-bit word, and not "250 nS for SPI management per data byte transfer". With 50 CPU cycles per complete interrupt-based processing of two data bytes, the minimum CPU cycle duration needs to be 40 ns (25 MHz). With 10 DMA clocks per complete DMA-based processing of two data bytes, the minimum DMA clock duration needs to be 200 ns (5 MHz). More advanced SPI controllers are available. Freescale QSPI controller has the data buffer of 16 entries, 16 bytes each. In case of no idle between the SPI packets, either the interrupt or the DMA burst can be triggered for 128-byte portion of the data stream: each 128 us.

    • Sorry for the phrase "The critical design problem of decomposition the desired system into a few concurrently running subsystems is omitted in the article". This problem is described in part 2 of the article.

    • How the described nice programming technique can be used to implement a non-trivial embedded system? Typically, such a system must to react in real-time to events, which are belong to a few independent (weakly coupled) tasks (processes). The critical design problem of decomposition the desired system into a few concurrently running subsystems is omitted in the article. The article suggests hierarchical processing of the events. The excessive real-time penalty of hierarchical message processing is prohibitive for the critical system events.

    • The approach "one architecture fits all control levels" is doubtful. 8-bit MCU are optimized for simple sensors and actuators. DSP is optimized for matrix algorithms like processing motor voltage/current waveforms. 32-bit MCU are optimized for some mix of networking, intensive calculation, and sophisticated logic, which is commonly presents in PLC. General purpose microprocessors are best for GUI and other high level tasks. Attempt to use the same core architecture for any task leads to inefficient implementation of each task.

    • You underestimate before-microprocessor technologies. Example of advanced devices without microcontrollers: Computers - mainframe, supercomputers, minicomputers. Actually, only personal computers are missing. Vehicles - almost the same as now, excluding nice, but not vital systems: ABS, advanced ignition, computerized gearbox. Aircraft - hude quantity of excellent planes. Internet - as university and military oriented networks using most of today's internet technologies.

    • One more hardware interface for video and multimedia? Think about below non-complete list of non-comatible already existing video interfaces: - Full TV signal (with or without Hyperband, PAL, SECAM, NTSC) - Direct video input - VGA family (with or without Plag&Play) - S-video - USB 2.0 - FireWire As a consumer, I'd say: Enough! Why the manufacturess still didn't learned the long-term result of missing commonly agreed video interface? Now think about the following example of well-designed hardware interface. Remember, when Ethernet/802.3 network interface was invented? It is still excellent - with all the generations of the network technologies.

    • The author writes: "Anecdotal newsgroup discussions report space and performance efficiency losses of between 8 percent and 30 percent for C++ implementations. Of course, for the exact same code using the same C library, we expect identical binary code." Below is a real-life example of a huge C++ inefficiency. One time I used perfectly written (I checked the sourse code) library C++ class to set 0/1 at I/O pins of Coldfire 5270 microcontroller. The used function has single drawback: 19 us to set either 1 or 0 - with 147 MHz of the core frequency. I created specialized C inline function, which only write to the needed registers. This implementation took only 0.5 us to change state of the pin.