MP Divakar

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Vice President

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    • This article's title "A brief primer on embedded SoC packaging options" is rather misleading... there is nothing here that addresses what is unique or challenging to embedded SoC. Almost all of the material is a summary of packaging options for a generic SoC. Some of the definitions/issues with respect to signal noise (jitter, cross talk, etc.) leaves me wondering what the authors were trying to accomplish here! These things are better defined and explained in books (like the one Dr. Howard Johnson!). MP Divakar

    • @VortexKannan: it works fine! Make sure you have turned on the plugins for Acrobat Reader in your browser. MP Divakar

    • @Ron Wilson: great summary, probably the only one (that I have read) on this topic to shed some light on what the marriage means to customers as well as EDA vendors. Maneuvers by Ansys in the EDA business was well expected at the last DAC floor (where Ansys wasn't even present!) that there were rumours about several EDA companies. One of the benefits companies like Ansys can potentially bring to the design flow of 3DIC is physics-based simulation to drive design decisions early on. To that end, I believe there are opportunities for innovations that non-traditional EDA companies like Ansys can best serve to the industry's benefit. MP Divakar

    • @Ron Wilson: thank you for the "brutally honest" assessment of 3D IC's & EDA -the comment "until there is an integrated flow there won't be a large market..." nails it! I have many comments on Michael Demler's article but I shall do that at another time. I would argue the 2.5D using Si interposers will lead the market for a while, till TSV-enabled multiple stacks of substrates become commonplace. The drivers for these are several: 1. There is simply not enough space to connect chip packages with a large number of I/O's to the board -the design rules in board layout are limiting, most at 3mil width/spacing. So multiple dice have to co-habit the same substrate in a BGA package. This chip-to-chip driver interconnecting will drive a number of communication IC products for a foreseeable future. This is where the Xilinx's, Altera's will put their effort as you also note. 2. Diminishing latency budget in chip-to-chip communication: examples abound in 40G/100G backplane market, another driver for integrating multiple substrates of IC's that interconnect with each other and are challenged by the prop delays by having to go thru a long, challenging paths. Si interposers provide the most optimum way to interconnect between chips. 3. Integration of passives, including planar magnetics: inductors and capacitors for bypassing / decoupling, power management functions, etc., are easier to to implement with Si interposers. Dr. MP Divakar

    • Dr. Rhines points about the differences design practices between substrates and IC layouts are valid, as are the test concerns on products assembled with KGD's. @deans_#1: many challenges in 3D stacked using TSV's like capacitive & inductive coupling will not go away even in monolithic designs too. But the cost of handling them in monolithic designs may be lower. Dr. MP Divakar

    • I seriously doubt if the industry has the appetite for another type of interconnect based on PCIe! Ethernet is firmly in the leading place and will most likely stay that we way for many years to come. Besides, there are many companies (like Cisco, Arista, etc) that offer switches for CEE using SFP+ interconnects for SAN & LAN consolidation and virtualization. This is also finding market acceptance. The author makes no mention of protocol off loading engines to deal with any perceived latency problems. The TCP/IP offload engines are already offered by some companies (Chelsea Inc)that alleviate the latency issues. For financial markets where round trip latency is an issue to be addressed, IB has been serving quite well. I don't see how PCIe can disrupt this market. PCIx standards should stay at the mother board levels, IMHO! Dr. MP Divakar

    • It would seem that we can deploy a group of sensors with each sensor configured to do a certain sensing function based on its ability to balance the demands of sensing and communication against the power available. So it is largely a system design problem that should make use of the available power (whether harvested with vibrations, solar, ambient EMI, etc) to the max. MP Divakar

    • @Bob Scannell: regarding the block diagram in the article for the inertial navigation system, you may already know this -the acceleration and the rotation rate sensors can be accomplished by one set of g-sensors, positioned and configured strategically! I proposed a system like that more than a decade ago for an anti-rollover system in an automobile. Note also that it is relatively straightforward to deploy a sensor network in M2M configuration that can extend GPS output in places where GPS is denied! Overall, it is a good summary article... MP Divakar

    • I am a bit puzzled here... the author seems to be making the case for marketing a cryptographic security IC for the purpose of ensuring 'security' of the smart grid, from a networking perspective. But the existing hardware and software security technologies of communication networks (though not fool proof) seem to be doing an adequate job without having to use "cryptographic security IC!" More over, the approach he is describing of flushing security keys at frequent intervals can be implemented at several layers using the existing resources (like PHY for one!). Dr. MP Divakar

    • Well, many interconnectable products can be secured with a lockable mechanism. Take for example, the RJ45 patch cords which the US Government requires to be secured to a device that it connects, many cases VoIP phones and network devices in defense and other high security establishments. It is not at all difficult to extend the securing mechanism to USB interconnects as well. It will come down to the price premiums one has to pay for added security. Dr. MP Divakar